Figure selleck inhibitor 1.(a) Schematic of material layer structure (cross-sectional view) and (b) schematic of device structure (top and cross-sectional view).As shown in Figure 1(a), the epitaxial structure consists of a 30-nm-thick GaN buffer layer, a 2-��m-thick undoped GaN layer and 25-nm-thick undoped-AlGaN barrier layer with an Al composition of 25%. The electron Inhibitors,Modulators,Libraries mobility and carrier sheet density of the two dimensional electron gas (2DEG) are 1,860 cm2/Vsec and 6.61 �� 1012 cm?2, respectively, at room temperature. The GaN buffer is basically necessary to achieve a uniform Ga face polarity of the GaN epilayer across the entire substrate and also improves the structural quality of the following GaN-layer.The schematic of the device structure is shown in Figure 1(b).
The device fabrication process starts with 100-nm-thick SiO2 Inhibitors,Modulators,Libraries deposition using plasma-enhanced chemical vapour deposition (PECVD) at 280 ��C with a SiH4/NH3/He gas system. This SiO2 dielectric layer plays a role as a mask for channel mesa formation in the following dry etching process. This dielectric mask layer is removed after that. A mesa etching is formed using inductive-coupled plasma Inhibitors,Modulators,Libraries (ICP)-assisted reactive ion beam etching with a Cl-based gas system consisting of BCl3, Cl2 and Ar. The etching pressure is 5 mTorr and the etching rate is around 0.1 ��m/min. The drain and source electrodes are formed by deposition of Ti/Al/Ti/Au (20 nm/50 nm/20 nm/150 nm) multilayers, annealing process at 850 ��C for 30 s under a flowing of N2 ambient by rapid thermal annealing system, and conventional lift off process.
Although the present device is a two-terminal Inhibitors,Modulators,Libraries device, electrodes are called source and drain electrodes in this article so that the results on an open gated device, also known as a gateless device, can be correlated with the behavior of the gated device. The drain will be positively biased, and the voltage and current are called the drain-source voltage, VDS, and drain-source current, IDS, respectively.Next, the device surface is covered with 300-nm-thick SiO2 film using PECVD to prevent a chemical reaction between electrolyte and metal electrodes. Finally, the open-gate area, width, W of 490 ��m and length, L of 40 ��m, is defined through standard photolithography and wet etching processes in a buffered HF solution. The oxide layer is believed to be removed at this stage.
However, a very thin oxide layer may be formed naturally after being exposed to the air. Since the experiment is done in the HCl-contained electrolyte, such a thin native oxide layer shall be etched Anacetrapib out upon immersing in the electrolyte . Therefore, the effect of native oxide layer on the sensing response is neglected in this study. The fabricated device is shown Vandetanib mw in Figure 2.Figure 2.Photo of fabricated device (top view).Figure 3(a) shows a photo and schematic of sample holder.